Learning the Art of Electronics: 19L.1.4 Schematic of Reaction Timer FSM

In addition to the 74HC175 quad D flip-flop used to hold the state information, we were able to implement both the output and the next state logic with only two gate packages through judicious use of DeMorgan’s Theorem: a 74HC10 triple 3-input NAND and a 74HC02 quad NOR.